1. Field of the Invention
This invention relates generally to a method for fabricating semiconductor devices and the devices so formed, and specifically to a method for forming isolation regions after formation of a gate electrode and the semiconductor devices so formed.
2. Related Art
In the manufacture of high performance Metal On Semiconductor (MOS) and combined Bipolar and MOS (BiMOS) semiconductor devices, each individual device structure is typically electrically isolated from other device structures through an isolation region. Formation of such isolation regions generally falls into two major categories. The first category encompasses all of the variations of LOCOS (LOCal Oxidation of Silicon) and involves exposing silicon to an oxidizing atmosphere to form silicon oxide. The second category includes the various trench forming and filling isolation structures, and thus requires etching a portion of the substrate and then refilling the etched portion with a dielectric material.
The LOCOS methods all involve conversion of a portion of the silicon substrate to a silicon oxide film in an oxidizing atmosphere, typically steam at approximately 1000.degree. C. (degrees Centigrade). This conversion or oxidation process is restricted to predetermined areas of the substrate through the use of an oxidation resistant layer overlying the substrate, where only the predetermined areas are exposed. However, despite their broad application, LOCOS based processes all have several drawbacks. The first of these drawbacks is the formation of a "Bird's Beak" region under a portion of the oxidation resistant layer or mask. While variations of the basic LOCOS process, in particular Poly-Buffer LOCOS (PBL), have served to reduce the size of the "Bird's Beak" region, "Bird's Beak" formation can still restrict the usefulness of such LOCOS processes for deep sub-micron devices (below about 0.5 .mu.m (micron)). In addition, the formation of the "Bird's Beak" region creates stress in the silicon substrate as the nitride masking layer is separated from the substrate. Also, as thermal oxidation of silicon is the conversion of a volume of silicon to approximately two times that volume of silicon oxide, the resulting structure is non-planar. Finally, the various LOCOS processes suffer from oxide thinning. That is, the thickness of the oxide film grown in any specific isolation region decreases with decreasing isolation width. For example, a field oxide that is grown to a thickness of 400 nm (nanometers) above a 1.5 .mu.m wide isolation region will be only 290 nm thick above a 0.8 .mu.m isolation region, a reduction in thickness of more than 25%. In 0.2 .mu.m isolation windows the thinning effect can be as large as 80%. Thus, the thickness of the isolation oxide formed can vary within a device. These drawbacks serve to limit the usefulness of LOCOS based isolation for semiconductor devices employing deep sub-micron design rules.
As a result, recent efforts have focused on trench isolation and in particular shallow trench isolation (STI) for semiconductor integrated circuits employing deep sub-micron design rules. STI eliminates two major problems of LOCOS type isolation schemes. First is the intrusion into active areas by the LOCOS "Bird's Beak". Thus, absent a "Bird's Beak" region, STI allows for smaller isolation spacing than that possible with LOCOS processes. In addition, as STI involves filling a photolithographically defined trench region with a dielectric material, oxide thinning is eliminated. Thus, STI allows for isolation regions of varying widths to be fabricated within a single circuit. However, STI process and structures have other drawbacks that limit their acceptance and usefulness for devices employing sub-micron design rules. Among these other drawbacks are the increased process complexity required to create such STI regions, inversion of vertical trench sidewalls of P-type active areas, less than adequate planarity of the resulting surface and stress induced by trench etching processes and by trench fill materials.
In addition to the physical requirement of smaller isolation region widths, deep sub-micron devices also require lower parasitic leakage currents and parasitic capacitance for optimum performance. One method for providing these lower leakage levels and capacitances is the formation of dielectrically isolated islands within a semiconductor substrate. For example, Varker et al. in U.S. Pat. No. 4,683,637 issued Aug. 4, 1987, form MOS transistors " . . . using the gate conductor to mask a high dose high energy implant which creates a thin dielectric region within the body of the common substrate beneath source and drain regions, but not beneath the channel region." (abstract). However, Varker et al. combines this thin dielectric region with lateral STI isolation regions. Thus while reducing parasitic leakage and capacitance, Varker et al. do not eliminate the above mentioned problems and drawbacks of such STI isolation regions.
Therefore, improved methods of forming isolation regions are needed for deep sub-micron semiconductor devices that will reduce and/or eliminate the effects of the problems associated with LOCOS or STI methods. In addition, these improved methods should result in an essentially planar device structure to enhance the manufacturability of such devices that employ deep sub-micron design rules. Improved methods, and structures thereof, are also needed that reduce or eliminate parasitic leakage and capacitance in such deep sub-micron semiconductor devices. Finally, the improved methods, and structures thereof, should provide reduced process complexity and manufacturing costs while resulting in increased device yields.